AMD EPYC generation guide: 7002 to 9005, sockets, memory channels and how to pick a SKU

A reference for the EPYC line as it appears in real quotes: which generation uses which socket, how memory channels and PCIe lanes change, what the 9005 SKU stack looks like, and how to read the F, P and c suffixes.

EPYC generations are not drop-in interchangeable, and the socket is only half the story. This is the shape of the line as we source it.

Generations and sockets

• SP3 covers 7002 and 7003, so a Rome platform can often take Milan with a BIOS update. Confirm with the server vendor's CPU support list, not the socket alone.
• SP5 covers 9004 and 9005. The move from SP3 to SP5 changes the board, the memory generation and the channel count, so it is a platform change, not an upgrade.
• 9005 uses Zen 5 and Zen 5c: up to 128 cores with classic Zen 5 cores, up to 192 cores with dense Zen 5c cores.

Reading the SKU

• Four digits then an optional letter. Higher first digits are newer generations; the middle digits track core count and tier.
• P suffix means single-socket only, and it is materially cheaper. If the workload never needs two sockets, this is free money.
• F suffix means frequency-optimised: fewer cores, higher clocks, larger cache per core. This is the choice for per-core licensed software and latency-sensitive workloads.
• c in the family name (Zen 5c dense cores) means very high core counts at lower clocks, aimed at scale-out and containers.

Selected EPYC 9005 SKUs

• 9005 supports DDR5 at up to 6000 to 6400 MT/s depending on SKU and platform, across 12 channels per socket.
• 160 PCIe Gen5 lanes are available on 2P configurations, 128 on some single-socket parts.
• TDPs up to 500 W per socket mean airflow and power budget become real design constraints in 1U.

How to choose

• Per-core licensed software (databases, some hypervisors, some VDI): take an F-series or a lower core count at higher clock. The licence cost dominates the hardware cost.
• Virtualisation and container density: take the highest core count you can cool and populate all 12 memory channels.
• Single-socket workloads: check the P SKUs first. One socket with 12 channels and 128 lanes replaces a lot of older dual-socket boxes.
• Always populate one DIMM per channel where you can. A 12-channel CPU with 8 DIMMs is running with a third of its bandwidth unused.

The ETON view

EPYC is where the largest consolidation savings currently sit, and the reason is memory channels rather than cores. A single-socket 9004 or 9005 node with all 12 channels populated will replace two older dual-socket nodes on most virtualisation estates, which halves socket-based licensing, cuts rack space and usually reduces total power despite the higher per-socket TDP.

The practical constraint is thermal. 400 to 500 W sockets are not a straightforward 1U proposition, and specifying dense cores into a hall provisioned for 6 kW racks is how projects stall. We would rather size the platform to the cooling you actually have.

There is also a strong second-hand argument: 7003 Milan on SP3 is inexpensive, plentiful, and still 8 channels of DDR4 with PCIe Gen4. For a hosting tier or a lab, it is often the better cost per useful core. Tell us the licence model and the rack power and we will price both routes.

Related infrastructure

• Processors
• HPE Rack Servers
• Dell PowerEdge Rack Servers
• Data Centre Solutions

Category: Servers · Vendor: AMD · Technology: EPYC 7002 / 7003 / 9004 / 9005, SP3 and SP5 sockets · Last verified: 09 Sep 2026 · ~3 min read

Sourcing this kind of infrastructure? Talk to ETON about availability, lead time and pricing.